FIG. 1 is a schematic circuit diagram illustrating a conventional non-volatile memory. As shown in FIG. 1, the non-volatile memory comprises a memory array, a row decoder 110, a column decoder 130, and a sensing circuit 140. The row decoder 110 is connected with m word lines WL1˜WLm. The column decoder 130 is connected with n bit lines BL1˜BLn.
Moreover, the memory array is connected with the m word lines WL1˜WLm, the n bit lines BL1˜BLn and a source line SL. The memory array comprises m×n memory cells C11˜Cmn. Each of the memory cells comprises a floating gate transistor. Moreover, each of the memory cells is connected with the corresponding word line, the corresponding bit line and the source line SL. Take the memory cell C11 as an example. The control gate terminal of the floating gate transistor is connected with the word line WL1, the drain terminal of the floating gate transistor is connected with the bit line BL1, and the source terminal of the floating gate transistor is connected with the source line SL.
Generally, the storing state of the memory cell is determined according to the amount of the hot carriers (or charges) stored in the floating gate of the floating gate transistor. For example, if the hot carriers are injected into the floating gate, the memory cell has a first storing state (e.g. the storing state “0”). Whereas, if no hot carriers are injected into the floating gate, the memory cell has a second storing state (e.g. the storing state “1”).
The column decoder 130 comprises n switch transistors My1˜Myn. According to a column control signal Y[1:n], the column decoder 130 generates n column switch signals Y1˜Yn. According to the n column switch signals Y1˜Yn, one of the n switch transistors My1˜Myn is in a close state but the others of the n switch transistors My1˜Myn are in an open state.
Generally, during a read cycle, the row decoder 110 enables a word line to determine a selected row of n memory cells. Moreover, according to the column control signal Y[1:n], the column decoder 130 determines a selected memory cell from the selected row of n memory cells. Then, the sensing circuit 140 judges the storing state of the selected memory cell.
For example, if the word line WL2 is enabled by the row decoder 110, the second row of memory cells are determined. That is, one of the n memory cells C21˜C2n will be determined as the selected memory cell. Moreover, if the column switch signal Y1 is enabled, only the switch transistor My1 is in the close state but the other switch transistors My2˜Myn are in the open state. Under this circumstance, the bit line BL1 is connected with a data line DL, but the other bit lines BL2˜BLn are not connected with the data line DL. Consequently, the memory cell C21 is the selected memory cell, and the sensing circuit 140 further judges the storing state of the selected memory cell.
As shown in FIG. 1, the sensing circuit 140 comprises a transistor Mn1, a transistor Mn2, a transistor Mp1, an operation amplifier OP1 and an operation amplifier OP2.
The source terminal of the transistor Mp1 is connected with a first supply voltage source Vdd (e.g. 3.3V). The gate terminal of the transistor Mp1 receives a bias voltage Vbias. The drain terminal of the transistor Mp1 is connected with a node b. Consequently, the transistor Mp1 is served as a reference current source for generating a reference current Iref to the node b.
The drain terminal of the transistor Mn1 and the data line DL are connected with a node a. The gate terminal of the transistor Mn1 is connected with a node c. The source terminal of the transistor Mn1 is connected with a second supply voltage source Vss (e.g. a ground voltage GND). The drain terminal of the transistor Mn2 is connected with the node b. The gate terminal of the transistor Mn2 is connected with the node c. The source terminal of the transistor Mn2 is connected with the second supply voltage source Vss.
A positive input terminal of the operation amplifier OP1 is connected with the node a. A negative input terminal of the operation amplifier OP1 receives a comparing voltage VDL (e.g. 0.4V). An output terminal of the operation amplifier OP1 is connected with the node c. Consequently, a current mirror is defined by the transistor Mn1, the transistor Mn2 and the operation amplifier OP1. The drain terminal of the transistor Mn1 is an input terminal of the current mirror for inputting a cell current Icell. The drain terminal of the transistor Mn2 is a mirroring terminal for generating a mirroring current.
A positive input terminal of the operation amplifier OP2 is connected with the node a. A negative input terminal of the operation amplifier OP2 is connected with the node b. An output terminal of the operation amplifier OP2 generates an output signal OUT to indicate the storing state of the selected memory cell. The principle of judging the storing state of the selected memory cell by the sensing circuit 140 will be illustrated as follows.
For realizing the storing state of the memory cell C21 during the read cycle, the source line SL is firstly pre-charged to a source line voltage VSL (e.g. 2V). Then, the word line WL2 is enabled by the row decoder 110 and the column switch signal Y1 is enabled by the column decoder 130. Consequently, the selected memory cell C21 is determined.
FIG. 2 is a schematic circuit diagram illustrating the relationship between the sensing circuit and the selected memory cell C21 of the conventional non-volatile memory. The principles of judging the storing state of the selected memory cell C21 by the sensing circuit 140 will be illustrated as follows. In the case that the memory cell C21 is the selected memory cell, the switch transistor My1 is in the close state and the bit line BL1 is connected with the data line DL. Consequently, the cell current Icell generated by the selected memory cell C21 is transmitted from the bit line BL1 to the data line DL through the switch transistor My1, and then inputted into the sensing circuit 140.
When the sensing circuit 140 starts to receive the cell current Icell, the voltage Va at the node a (i.e. the voltage at the data line DL) is discharged from the source line voltage VSL to the comparing voltage VDL. Moreover, when the voltage Va at the node a is discharged to the comparing voltage VDL, the voltage Va at the node a and the voltage Vb at the node b are compared with each other by the operation amplifier OP2. Consequently, the operation amplifier OP2 generates the output signal OUT to indicate the storing state of the selected memory cell C21.
For example, if the selected memory cell C21 has the first storing state (e.g. the storing state “0”), the cell current Icell is higher than the reference current Iref. When the voltage Va at the node a is discharged to the comparing voltage VDL, the voltage Vb at the node b is discharged to a magnitude near the second supply voltage source Vss. Under this circumstance, the voltage Va at the node a is higher than the voltage Vb at the node b. Consequently, the output signal OUT from the operation amplifier OP2 is in a high level state to indicate that the storing state of the selected memory cell C21 is the first storing state.
On the other hand, if the selected memory cell C21 has the second storing state (e.g. the storing state “1”), the cell current Icell is lower than the reference current Iref. When the voltage Va at the node a is discharged to the comparing voltage VDL, the voltage Vb at the node b is maintained at a magnitude near the first supply voltage source Vdd. Under this circumstance, the voltage Va at the node a is lower than the voltage Vb at the node b. Consequently, the output signal OUT from the operation amplifier OP2 is in a low level state to indicate that the storing state of the selected memory cell C21 is the second storing state.
From the above discussions, during the read cycle of the conventional non-volatile memory, the storing state of the selected memory cell C21 can be realized according to the output signal OUT. However, until the voltage Va at the node a (i.e. the voltage at the data line DL) is discharged to the comparing voltage VDL, the sensing circuit 140 compares the voltage Va at the node a and the voltage Vb at the node b so as to generate the output signal OUT.
In other words, there is a delaying time Td between the start time point of the read cycle and the time point of generating the output signal OUT. After the components of the delaying time Td are analyzed, the following analyzing result is obtained. For example, the delaying period caused by the operations of the row decoder 110 and the column decoder 130 is about 0.2209×Td, the delaying period caused by the discharging time of the data line DL is about 0.4244×Td, and the delaying period caused by the operations of the sensing circuit 140 is about 0.3547×Td.
Obviously, during the read cycle of the conventional non-volatile memory, if the discharging time of the data line DL is too long, the access time of the memory cell is increased. In other words, if the discharging time of the data line DL is shortened, the read speed of the memory cell can be effectively enhanced.